Conventional devices such as microprocessors and graphics processors typically rely on edge-triggered flip-flops for pipelining datapaths and for implementing sequential logic. When the logic between two edge-triggered flip-flops has a small delay, specifically when the delay approaches the hold time needed for proper operation, additional circuitry is inserted into the path by timing tools to fix the hold time violations. Other than to ensure that hold time violations are fixed, the insertion of additional circuitry is undesirable because of the additional circuitry occupies space on the die and consumes power during operation.
Thus, there is a need for reducing hold time violations and/or addressing other issues associated with the prior art.